1-1 Comparison of Performance Per Pin for Various Buses
1-2 33 MHz PCI Bus Based Platform
1-3 Typical PCI Burst Memory Read Bus Cycle
1-4 33 MHz PCI Based System Showing Implementation of a PCI-to-PCI Bridge
1-5 PCI Transaction Model
1-6 PCI Bus Arbitration
1-7 PCI Transaction Retry Mechanism
1-8 PCI Transaction Disconnect Mechanism
1-9 PCI Interrupt Handling
1-10 PCI Error Handling Protocol
1-11 Address Space Mapping
1-12 PCI Configuration Cycle Generation
1-13 256 Byte PCI Function Configuration Register Space
1-14 Latest Generation of PCI Chipsets
1-15 66 MHz PCI Bus Based Platform
1-16 66 MHz/133 MHz PCI-X Bus Based Platform
1-17 Example PCI-X Burst Memory Read Bus Cycle
1-18 PCI-X Split Transaction Protocol
1-19 Hypothetical PCI-X 2.0 Bus Based Platform
1-20 PCI Express Link
1-21 PCI Express Differential Signal
1-22 PCI Express Topology
1-23 Low Cost PCI Express System
1-24 Another Low Cost PCI Express System
1-25 PCI Express High-End Server System
2-1 Non-Posted Read Transaction Protocol
2-2 Non-Posted Locked Read Transaction Protocol
2-3 Non-Posted Write Transaction Protocol
2-4 Posted Memory Write Transaction Protocol
2-5 Posted Message Transaction Protocol
2-6 Non-Posted Memory Read Originated by CPU and Targeting an Endpoint
2-7 Non-Posted Memory Read Originated by Endpoint and Targeting Memory
2-8 IO Write Transaction Originated by CPU, Targeting Legacy Endpoint
2-9 Memory Write Transaction Originated by CPU, Targeting Endpoint
2-10 PCI Express Device Layers
2-11 TLP Origin and Destination
2-12 TLP Assembly
2-13 TLP Disassembly
2-14 DLLP Origin and Destination
2-15 DLLP Assembly
2-16 DLLP Disassembly
2-17 PLP Origin and Destination
2-18 PLP or Ordered-Set Structure
2-19 Detailed Block Diagram of PCI Express Device's Layers
2-20 TLP Structure at the Transaction Layer
2-21 Flow Control Process
2-22 Example Showing QoS Capability of PCI Express
2-23 TC Numbers and VC Buffers
2-24 Switch Implements Port Arbitration and VC Arbitration Logic
2-25 Data Link Layer Replay Mechanism
2-26 TLP and DLLP Structure at the Data Link Layer
2-27 Non-Posted Transaction on Link
2-28 Posted Transaction on Link
2-29 TLP and DLLP Structure at the Physical Layer
2-30 Electrical Physical Layer Showing Differential Transmitter and Receiver
2-31 Memory Read Request Phase
2-32 Completion with Data Phase
3-1 Multi-Port PCI Express Devices Have Routing Responsibilities
3-2 PCI Express Link Local Traffic: Ordered Sets
3-3 PCI Express Link Local Traffic: DLLPs
3-4 PCI Express Transaction Request And Completion TLPs
3-5 Transaction Layer Packet Generic 3DW And 4DW Headers
3-6 Generic System Memory And IO Address Maps
3-7 3DW TLP Header Address Routing Fields
3-8 4DW TLP Header Address Routing Fields
3-9 Endpoint Checks Routing Of An Inbound TLP Using Address Routing
3-10 Switch Checks Routing Of An Inbound TLP Using Address Routing
3-11 3DW TLP Header ID Routing Fields
3-12 4DW TLP Header ID Routing Fields
3-13 Switch Checks Routing Of An Inbound TLP Using ID Routing
3-14 4DW Message TLP Header Implicit Routing Fields
3-15 PCI Express Devices And Type 0 And Type 1 Header Use
3-16 PCI Express Configuration Space Type 0 and Type 1 Headers
3-17 32-Bit Prefetchable Memory BAR Set Up
3-18 64-Bit Prefetchable Memory BAR Set Up
3-19 IO BAR Set Up
3-20 6GB, 64-Bit Prefetchable Memory Base/Limit Register Set Up
3-21 2MB, 32-Bit Non-Prefetchable Base/Limit Register Set Up
3-22 IO Base/Limit Register Set Up
3-23 Bus Number Registers In A Switch
4-1 TLP And DLLP Packets
4-2 PCI Express Layered Protocol And TLP Assembly/Disassembly
4-3 Generic TLP Header Fields
4-4 Using First DW and Last DW Byte Enable Fields
4-5 Transaction Descriptor Fields
4-6 System IO Map
4-7 3DW IO Request Header Format
4-8 3DW And 4DW Memory Request Header Formats
4-9 3DW Configuration Request And Header Format
4-10 3DW Completion Header Format
4-11 4DW Message Request Header Format
4-12 Data Link Layer Sends A DLLP
4-13 Generic Data Link Layer Packet Format
4-14 Ack Or Nak DLLP Packet Format
4-15 Power Management DLLP Packet Format
4-16 Flow Control DLLP Packet Format
4-17 Vendor Specific DLLP Packet Format
5-1 Data Link Layer
5-2 Overview of the ACK/NAK Protocol
5-3 Elements of the ACK/NAK Protocol
5-4 Transmitter Elements Associated with the ACK/NAK Protocol
5-5 Receiver Elements Associated with the ACK/NAK Protocol
5-6 Ack Or Nak DLLP Packet Format
5-7 Example 1 that Shows Transmitter Behavior with Receipt of an ACK DLLP
5-8 Example 2 that Shows Transmitter Behavior with Receipt of an ACK DLLP
5-9 Example that Shows Transmitter Behavior on Receipt of a NAK DLLP
5-10 Table and Equation to Calculate REPLAY_TIMER Load Value
5-11 Example that Shows Receiver Behavior with Receipt of Good TLP
5-12 Example that Shows Receiver Behavior When It Receives Bad TLPs
5-13 Table to Calculate ACKNAK_LATENCY_TIMER Load Value
5-14 Lost TLP Handling
5-15 Lost ACK DLLP Handling
5-16 Lost ACK DLLP Handling
5-17 Switch Cut-Through Mode Showing Error Handling
6-1 Example Application of Isochronous Transaction
6-2 VC Configuration Registers Mapped in Extended Configuration Address Space
6-3 The Number of VCs Supported by Device Can Vary
6-4 Extended VCs Supported Field
6-5 VC Resource Control Register
6-6 TC to VC Mapping Example
6-7 Conceptual VC Arbitration Example
6-8 Strict Arbitration Priority
6-9 Low Priority Extended VC Count
6-10 Determining VC Arbitration Capabilities and Selecting the Scheme
6-11 VC Arbitration with Low-and High-Priority Implementations
6-12 Weighted Round Robin Low-Priority VC Arbitration Table Example
6-13 VC Arbitration Table Offset and Load VC Arbitration Table Fields
6-14 Loading the VC Arbitration Table Entries
6-15 Example Multi-Function Endpoint Implementation with VC Arbitration
6-16 Port Arbitration Concept
6-17 Port Arbitration Tables Needed for nEach VC
6-18 Port Arbitration Buffering
6-19 Software checks Port Arbitration Capabilities and Selects the Scheme to be Used
6-20 Maximum Time Slots Register
6-21 Format of Port Arbitration Table
6-22 Example of Port and VC Arbitration within A Switch
7-1 Location of Flow Control Logic
7-2 Flow Control Buffer Organization
7-3 Flow Control Elements
7-4 Types and Format of Flow Control Packets
7-5 Flow Control Elements Following Initialization
7-6 Flow Control Elements Following Delivery of First Transaction
7-7 Flow Control Elements with Flow Control Buffer Filled
7-8 Flow Control Rollover Problem
7-9 Initial State of Example FC Elements
7-10 INIT1 Flow Control Packet Format and Contents
7-11 Devices Send and Initialize Flow Control Registers
7-12 Device Confirm that Flow Control Initialization is Completed for a Given Buffer
7-13 Flow Control Update Example
7-14 Update Flow Control Packet Format and Contents
8-1 Example of Strongly Ordered Transactions that Results in Temporary Blocking
9-1 Native PCI Express and Legacy PCI Interrupt Delivery
9-2 64-bit MSI Capability Register Format
9-3 32-bit MSI Capability Register Set Format
9-4 Message Control Register
9-5 Device MSI Configuration Process
9-6 Format of Memory Write Transaction for Native-Deive MSI Delivery
9-7 Interrupt Pin Register within PCI Configuration Header
9-8 INTx Signal Routing is Platform Specific
9-9 Configuration Command Register — Interrupt Disable Field
9-10 Configuration Status Register — Interrupt Status Field
9-11 Legacy Devices Use INTx Messages Virtualize INTA#-INTD# Signal Transitions
9-12 Switch Collapses INTx Message to Achieve Wired-OR Characteristics
9-13 INTx Message Format and Types
9-14 PCI Express System with PCI-Based IO Controller Hub
10-1 The Scope of PCI Express Error Checking and Reporting
10-2 Location of PCI Express Error-Related Configuration Registers
10-3 The Error/Poisoned Bit within Packet Headers
10-4 Basic Format of the Error Messages
10-5 Completion Status Field within the Completion Header
10-6 PCI-Compatible Configuration Command Register
10-7 PCI-Compatible Status Register (Error-Related Bits)
10-8 PCI Express Capability Register Set
10-9 Device Control Register Bit Fields Related to Error Handling
10-10 Device Status Register Bit Fields Related to Error Handling
10-11 Link Control Register Allows Retraining of Link
10-12 Link Retraining Status Bits within the Link Status Register
10-13 Root Control Register
10-14 Advanced Error Capability Registers
10-15 The Advanced Error Capability & Control Register
10-16 Advanced Correctable Error Status Register
10-17 Advanced Correctable Error Mask Register
10-18 Advanced Uncorrectable Error Status Register
10-19 Advanced Uncorrectable Error Severity Register
10-20 Advanced Uncorrectable Error Mask Register
10-21 Root Error Status Register
10-22 Advanced Source ID Register
10-23 Advanced Root Error Command Register
10-24 Error Handling Flow Chart
11-1 Physical Layer
11-2 Logical and Electrical Sub-Blocks of the Physical Layer
11-3 Physical Layer Details
11-4 Physical Layer Transmit Logic Details
11-5 Transmit Logic Multiplexer
11-6 TLP and DLLP Packet Framing with Start and End Control Characters
11-7 x1 Byte Striping
11-8 x4 Byte Striping
11-9 x8, x12, x16, x32 Byte Striping
11-10 x1 Packet Format
11-11 x4 Packet Format
11-12 x8 Packet Format
11-13 Scrambler
11-14 Example of 8-bit Character of 00h Encoded to 10-bit Symbol
11-15 Preparing 8-bit Character for Encode
11-16 8-bit to 10-bit (8b/10b) Encoder
11-17 Example 8-bit/10-bit Encodings
11-18 Example 8-bit/10-bit Transmission
11-19 SKIP Ordered-Set
11-20 Physical Layer Receive Logic Details
11-21 Receiver Logic's Front End Per Lane
11-22 Receiver's Link De-Skew Logic
11-23 8b/10b Decoder per Lane
11-24 Example of Delayed Disparity Error Detection
11-25 Example of x8 Byte Un-Striping
12-1 Electrical Sub-Block of the Physical Layer
12-2 Differential Transmitter/Receiver
12-3 Receiver DC Common Mode Voltage Requirement
12-4 Receiver Detection Mechanism
12-5 Pictorial Representation of Differential Peak-to-Peak and Differential Peak Voltages
12-6 Electrical Idle Ordered-Set
12-7 Transmission with De-emphasis
12-8 Problem of Inter-Symbol Interference
12-9 Solution is Pre-emphasis
12-10 LVDS (Low-Voltage Differential Signal) Transmitter Eye Diagram
12-11 Transmitter Eye Diagram Jitter Indication
12-12 Transmitter Eye Diagram Noise/Attenuation Indication
12-13 Screen Capture of a Normal Eye (With no De-emphasis Shown)
12-14 Screen Capture of a Bad Eye Showing Effect of Jitter, Noise and Signal Attenuation (With no De-emphasis Shown)
12-15 Compliance Test/Measurement Load
12-16 Receiver Eye Diagram
12-17 L0 Full-On Link State
12-18 L0s Low Power Link State
12-19 L1 Low Power Link State
12-20 L2 Low Power Link State
12-21 L3 Link Off State
13-1 PERST# Generation
13-2 TS1 Ordered-Set Showing the Hot Reset Bit
13-3 Secondary Bus Reset Register to Generate Hot Reset
13-4 Switch Generates Hot Reset on One Downstream Port
13-5 Switch Generates Hot Reset on All Downstream Ports
14-1 Link Training and Status State Machine Location
14-2 Example Showing Lane Reversal
14-3 Example Showing Polarity Inversion
14-4 Five Ordered-Sets Used in the Link Training and Initialization Process
14-5 Link Training and Status State Machine (LTSSM)
14-6 Detect State Machine
14-7 Polling State Machine
14-8 Configuration State Machine
14-9 Combining Lanes to form Links
14-10 Example 1 Link Numbering and Lane Numbering
14-11 Example 2 Link Numbering and Lane Numbering
14-12 Example 3 Link Numbering and Lane Numbering
14-13 Recovery State Machine
14-14 L0s Transmitter State Machine
14-15 L0s Receiver State Machine
14-16 L1 State Machine
14-17 L2 State Machine
14-18 Hot Reset State Machine
14-19 Disable State Machine
14-20 Loopback State Machine
14-21 Link Capabilities Register
14-22 Link Status Register
14-23 Link Control Register
15-1 System Allocated Bit
15-2 Elements Involved in Power Budget
15-3 Slot Power Limit Sequence
15-4 Power Budget Capability Registers
15-5 Power Budget Data Field Format and Definition
16-1 Relationship of OS, Device Drivers, Bus Driver, PCI Express Registers, and ACPI
16-2 Example of OS Powering Down All Functions On PCI Express Links and then the Links Themselves
16-3 Example of OS Restoring a PCI Express Function To Full Power
16-4 OS Prepares a Function To Cause System WakeUp On Device-Specific Event
16-5 PCI Power Management Capability Register Set
16-6 PCI Express Function Power Management State Transitions
16-7 PCI Function's PM Registers
16-8 Power Management Capabilities (PMC) Register - Read Only
16-9 Power Management Control/Status (PMCSR) Register - R/W
16-10 PM Registers
16-11 ASPM Link State Transitions
16-12 ASPM Support
16-13 Active State PM Control Field
16-14 Ports that Initiate L1 ASPM Transitions
16-15 Negotiation Sequence Required to Enter L1 Active State PM
16-16 Negotiation Sequence Resulting in Rejection to Enter L1 ASPM State
16-17 Switch Behavior When Downstream Component Signals L1 Exit
16-18 Switch Behavior When Upstream Component Signals L1 Exit
16-19 Example of Total L1 Latency
16-20 Config. Registers Used for ASPM Exit Latency Management and Reporting
16-21 Devices Transition to L1 When Software Changes their Power Level from D0
16-22 Software Placing a Device into a D2 State and Subsequent Transition to L1
16-23 Procedure Used to Transition a Link from the L0 to L1 State
16-24 Link States Transitions Associated with Preparing Devices for Removal of the Reference Clock and Power
16-25 Negotiation for Entering L2/L3 Ready State
16-26 State Transitions from L2/L3 Ready When Power is Removed
16-27 PME Message Format
16-28 WAKE# Signal Implementations
16-29 Auxiliary Current Enable for Devices Not Supporting PMEs
17-1 PCI Hot Plug Elements
17-2 PCI Express Hot-Plug Hardware/Software Elements
17-3 Hot Plug Control Functions within a Switch
17-4 PCI Express Configuration Registers Used for Hot-Plug
17-5 Attention Button and Hot Plug Indicators Present Bits
17-6 Slot Control Register Fields
17-7 Slot Status Register Fields
17-8 Location of Attention Button and Indicators
17-9 Hot-Plug Capability Bits for Server IO Modules
17-10 Hot Plug Message Format
18-1 PCI Express x1 connector
18-2 PCI Express Connectors on System Board
18-3 PERST Timing During Power Up
18-4 PERST# Timing During Power Management States
18-5 Example of WAKE# Circuit Protection
18-6 Presence Detect
18-7 PCI Express Riser Card
18-8 Mini PCI Express Add-in Card Installed in a Mobile Platform
18-9 Mini PCI Express Add-in Card Photo 1
18-10 Mini PCI Express Add-in Card Photo 2
19-1 Example System
19-2 Topology View At Startup
19-3 4KB Configuration Space per PCI Express Function
19-4 Header Type Register
20-1 A Function's Configuration Space
20-2 Configuration Address Port at 0CF8h
20-3 Example System
20-4 Peer Root Complexes
20-5 Type 0 Configuration Read Request Packet Header
20-6 Type 0 Configuration Write Request Packet Header
20-7 Type 1 Configuration Read Request Packet Header
20-8 Type 1 Configuration Write Request Packet Header
20-9 Example Configuration Access
21-1 Topology View At Startup
21-2 Example System Before Bus Enumeration
21-3 Example System After Bus Enumeration
21-4 Header Type Register
21-5 Capability Register
21-6 Header Type 0
21-7 Header Type 1
21-8 Peer Root Complexes
21-9 Multifunction Bridges in Root Complex
21-10 First Example of a Multifunction Bridge In a Switch
21-11 Second Example of a Multifunction Bridge In a Switch
21-12 Embedded Root Endpoint
21-13 Embedded Switch Endpoint
21-14 Type 0 Configuration Write Request Packet Header
21-15 RCRB Example
22-1 Header Type 0
22-2 Class Code Register
22-3 Header Type Register Bit Assignment
22-4 BIST Register Bit Assignment
22-5 Status Register
22-6 General Format of a New Capabilities List Entry
22-7 Expansion ROM Base Address Register Bit Assignment
22-8 Command Register
22-9 PCI Configuration Status Register
22-10 32-Bit Memory Base Address Register Bit Assignment
22-11 64-Bit Memory Base Address Register Bit Assignment
22-12 IO Base Address Register Bit Assignment
22-13 Header Type 1
22-14 IO Base Register
22-15 IO Limit Register
22-16 Example of IO Filtering Actions
22-17 Prefetchable Memory Base Register
22-18 Prefetchable Memory Limit Register
22-19 Memory-Mapped IO Base Register
22-20 Memory-Mapped IO Limit Register
22-21 Command Register
22-22 Bridge Control Register
22-23 Primary Interface Status Register
22-24 Secondary Status Register
22-25 Format of the AGP Capability Register Set
22-26 VPD Capability Registers
22-27 Chassis and Slot Number Registers
22-28 Main Chassis
22-29 Expansion Slot Register
22-30 Slot Capability Register
22-31 PCI Express Capabilities Register
22-32 Chassis Example One
22-33 Chassis Example Two
23-1 Expansion ROM Base Address Register Bit Assignment
23-2 Header Type Zero Configuration Register Format
23-3 Multiple Code Images Contained In One Device ROM
23-4 Code Image Format
23-5 AX Contents On Entry To Initialization Code
24-1 Function's Configuration Space Layout
24-2 PCI Express Capability Register Set
24-3 PCI Express Capabilities Register
24-4 Device Capabilities Register
24-5 Device Control Register
24-6 Device Status Register
24-7 Link Capabilities Register
24-8 Link Control Register
24-9 Link Status Register
24-10 Slot Capabilities Register
24-11 Slot Control Register
24-12 Slot Status Register
24-13 Root Control Register
24-14 Root Status Register
24-15 Enhanced Capability Header Register
24-16 Advanced Error Reporting Capability Register Set
24-17 Advanced Error Reporting Enhanced Capability Header
24-18 Advanced Error Capabilities and Control Register
24-19 Advanced Error Correctable Error Mask Register
24-20 Advanced Error Correctable Error Status Register
24-21 Advanced Error Uncorrectable Error Mask Register
24-22 Advanced Error Uncorrectable Error Severity Register
24-23 Advanced Error Uncorrectable Error Status Register
24-24 Advanced Error Root Error Command Register
24-25 Advanced Error Root Error Status Register
24-26 Advanced Error Uncorrectable and Uncorrectable Error Source ID Registers
24-27 Port and VC Arbitration
24-28 Virtual Channel Capability Register Set
24-29 VC Enhanced Capability Header
24-30 Port VC Capability Register 1 (Read-Only)
24-31 Port VC Capability Register 2 (Read-Only)
24-32 Port VC Control Register (Read-Write)
24-33 Port VC Status Register (Read-Only)
24-34 VC Resource Capability Register
24-35 VC Resource Control Register (Read-Write)
24-36 VC Resource Status Register (Read-Only)
24-37 Device Serial Number Enhanced Capability Header
24-38 Device Serial Number Register
24-39 EUI-64 Format
24-40 Power Budget Register Set
24-41 Power Budgeting Enhanced Capability Header
24-42 Power Budgeting Data Register
24-43 Power Budgeting Capability Register
24-44 RCRB Example
A-1 PCI Parallel Bus Start and End of a Transaction Easily Identified
A-2 PCI Express Serial Bit Stream
A-3 PCI Express Dual-Simplex Bus
A-4 Capturing All Patterns on PCI Express
A-5 Specific Trigger Definition for Upstream or Downstream Pair
A-6 Start with TS1
A-7 SKIP
A-8 Completion of 1024 TS1
A-9 Lane Number Declaration
A-10 Start of TS2
A-11 Initialization of Flow Control 1
A-12 Initialization of Flow Control 2
A-13 Flow Control Updates
A-14 Alternate Display in Listing Format
A-15 Mid-bus Pad Definition
A-16 Mid-Bus Suggested Signal Assignment
A-17 Exerciser Covering All Possible Commands
A-18 Exerciser Bit Level Manipulation Allowing Various Options
A-19 Supporting All Layers, Simultaneously
A-20 Jitter Analysis of a Transceiver source clock—Acceptable (for a specific device)
A-21 Jitter analysis of a Transceiver source clock—Unacceptable (for a specific device)
B--1 Migration from PCI to PCI Express
B--2 PCI Express in a Desktop System
B--3 PCI Express in a Server System
B--4 PCI Express in Embedded-Control Applications
B--5 PCI Express in a Storage System
B--6 PCI Express in Communications Systems
C--1 Enumeration Using Transparent Bridges
C--2 Direct Address Translation
C--3 Look Up Table Translation Creates Multiple Windows
C--4 Intelligent Adapters in PCI and PCI Express Systems
C--5 Host Failover in PCI and PCI Express Systems
C--6 Dual Host in a PCI and PCI Express System
C--7 Dual-Star Fabric
C--8 Direct Address Translation
C--9 Lookup Table Based Translation
C--10 Use of Limit Register
D--1 Class Code Register
E-1 Lock Sequence Begins with Memory Read Lock Request
E-2 Lock Completes with Memory Write Followed by Unlock Message
