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PCI Express System Architecture By  MindShare, Inc , Ravi Budruk, Don Anderson, Tom Shanley   Publisher : Addison Wesley Pub Date : September 04, 2003 ISBN : 0-321-15630-7 Pages : 1120

		Copyright
		Figures
		Tables
		Acknowledgments
		About This Book
			The MindShare Architecture Series
			Cautionary Note
			Intended Audience
			Prerequisite Knowledge
			Topics and Organization
			Documentation Conventions
			Visit Our Web Site
			We Want Your Feedback
		Part One.  The Big Picture
			Chapter 1.  Architectural Perspective
				This Chapter
				The Next Chapter
				Introduction To PCI Express
				Predecessor Buses Compared
				I/O Bus Architecture Perspective
				The PCI Express Way
				PCI Express Specifications
			Chapter 2.  Architecture Overview
				Previous Chapter
				This Chapter
				The Next Chapter
				Introduction to PCI Express Transactions
				PCI Express Device Layers
				Example of a Non-Posted Memory Read Transaction
				Hot Plug
				PCI Express Performance and Data Transfer Efficiency
		Part Two.  Transaction Protocol
			Chapter 3.  Address Spaces & Transaction Routing
				The Previous Chapter
				This Chapter
				The Next Chapter
				Introduction
				Two Types of Local Link Traffic
				Transaction Layer Packet Routing Basics
				Applying Routing Mechanisms
				Plug-And-Play Configuration of Routing Options
			Chapter 4.  Packet-Based Transactions
				The Previous Chapter
				This Chapter
				The Next Chapter
				Introduction to the Packet-Based Protocol
				Transaction Layer Packets
				Data Link Layer Packets
			Chapter 5.  ACK/NAK Protocol
				The Previous Chapter
				This Chapter
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				Reliable Transport of TLPs Across Each Link
				Elements of the ACK/NAK Protocol
				ACK/NAK DLLP Format
				ACK/NAK Protocol Details
				Error Situations Reliably Handled by ACK/NAK Protocol
				ACK/NAK Protocol Summary
				Recommended Priority To Schedule Packets
				Some More Examples
				Switch Cut-Through Mode
			Chapter 6.  QoS/TCs/VCs and Arbitration
				The Previous Chapter
				This Chapter
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				Quality of Service
				Perspective on QOS/TC/VC and Arbitration
				Traffic Classes and Virtual Channels
				Arbitration
			Chapter 7.  Flow Control
				The Previous Chapter
				This Chapter
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				Flow Control Concept
				Flow Control Buffers
				Introduction to the Flow Control Mechanism
				Flow Control Packets
				Operation of the Flow Control Model - An Example
				Infinite Flow Control Advertisement
				The Minimum Flow Control Advertisement
				Flow Control Initialization
				Flow Control Updates Following FC_INIT
			Chapter 8.  Transaction Ordering
				The Previous Chapter
				This Chapter
				The Next Chapter
				Introduction
				Producer/Consumer Model
				Native PCI Express Ordering Rules
				Relaxed Ordering
				Modified Ordering Rules Improve Performance
				Support for PCI Buses and Deadlock Avoidance
			Chapter 9.  Interrupts
				The Previous Chapter
				This Chapter
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				Two Methods of Interrupt Delivery
				Message Signaled Interrupts
				Legacy PCI Interrupt Delivery
				Devices May Support Both MSI and Legacy Interrupts
				Special Consideration for Base System Peripherals
			Chapter 10.  Error Detection and Handling
				The Previous Chapter
				This Chapter
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				Background
				Introduction to PCI Express Error Management
				Sources of PCI Express Errors
				Error Classifications
				How Errors are Reported
				Baseline Error Detection and Handling
				Advanced Error Reporting Mechanisms
				Summary of Error Logging and Reporting
		Part Three.  The Physical Layer
			Chapter 11.  Physical Layer Logic
				The Previous Chapter
				This Chapter
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				Physical Layer Overview
				Transmit Logic Details
				Receive Logic Details
				Physical Layer Error Handling
			Chapter 12.  Electrical Physical Layer
				The Previous Chapter
				This Chapter
				The Next Chapter
				Electrical Physical Layer Overview
				High Speed Electrical Signaling
				LVDS Eye Diagram
				Transmitter Driver Characteristics
				Input Receiver Characteristics
				Electrical Physical Layer State in Power States
			Chapter 13.  System Reset
				The Previous Chapter
				This Chapter
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				Two Categories of System Reset
				Reset Exit
				Link Wakeup from L2 Low Power State
			Chapter 14.  Link Initialization & Training
				The Previous Chapter
				This Chapter
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				Link Initialization and Training Overview
				Ordered-Sets Used During Link Training and Initialization
				Link Training and Status State Machine (LTSSM)
				Detailed Description of LTSSM States
				LTSSM Related Configuration Registers
		Part Four.  Power-Related Topics
			Chapter 15.  Power Budgeting
				The Previous Chapter
				This Chapter
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				Introduction to Power Budgeting
				The Power Budgeting Elements
				Slot Power Limit Control
				The Power Budget Capabilities Register Set
			Chapter 16.  Power Management
				The Previous Chapter
				This Chapter
				The Next Chapter
				Introduction
				Primer on Configuration Software
				Function Power Management
				Introduction to Link Power Management
				Link Active State Power Management
				Software Initiated Link Power Management
				Link Wake Protocol and PME Generation
		Part Five.  Optional Topics
			Chapter 17.  Hot Plug
				The Previous Chapter
				This Chapter
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				Background
				Hot Plug in the PCI Express Environment
				Elements Required to Support Hot Plug
				Card Removal and Insertion Procedures
				Standardized Usage Model
				Standard Hot Plug Controller Signaling Interface
				The Hot-Plug Controller Programming Interface
				Slot Numbering
				Quiescing Card and Driver
				The Primitives
			Chapter 18.  Add-in Cards and Connectors
				The Previous Chapter
				This Chapter
				The Next Chapter
				Introduction
				Form Factors Under Development
		Part Six.  PCI Express Configuration
			Chapter 19.  Configuration Overview
				The Previous Chapter
				This Chapter
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				Definition of Device and Function
				Definition of Primary and Secondary Bus
				Topology Is Unknown At Startup
				Each Function Implements a Set of Configuration Registers
				Host/PCI Bridge's Configuration Registers
				Configuration Transactions Are Originated by the Processor
				Configuration Transactions Are Routed Via Bus, Device, and Function Number
				How a Function Is Discovered
				How To Differentiate a PCI-to-PCI Bridge From a Non-Bridge Function
			Chapter 20.  Configuration Mechanisms
				The Previous Chapter
				This Chapter
				The Next Chapter
				Introduction
				PCI-Compatible Configuration Mechanism
				PCI Express Enhanced Configuration Mechanism
				Type 0 Configuration Request
				Type 1 Configuration Request
				Example PCI-Compatible Configuration Access
				Example Enhanced Configuration Access
				Initial Configuration Accesses
			Chapter 21.  PCI Express Enumeration
				The Previous Chapter
				This Chapter
				The Next Chapter
				Introduction
				Enumerating a System With a Single Root Complex
				Enumerating a System With Multiple Root Complexes
				A Multifunction Device Within a Root Complex or a Switch
				An Endpoint Embedded in a Switch or Root Complex
				Memorize Your Identity
				Root Complex Register Blocks (RCRBs)
				Miscellaneous Rules
			Chapter 22.  PCI Compatible Configuration Registers
				The Previous Chapter
				This Chapter
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				Header Type 0
				Header Type 1
				PCI-Compatible Capabilities
			Chapter 23.  Expansion ROMs
				The Previous Chapter
				This Chapter
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				ROM Purpose—Device Can Be Used In Boot Process
				ROM Detection
				ROM Shadowing Required
				ROM Content
				Execution of Initialization Code
				Introduction to Open Firmware
			Chapter 24.  Express-Specific Configuration Registers
				The Previous Chapter
				This Chapter
				Introduction
				PCI Express Capability Register Set
				PCI Express Extended Capabilities
				RCRB
		Appendices
			Appendix A.  Test, Debug and Verification
				Scope
				Serial Bus Topology
				Dual-Simplex
				Setting Up the Analyzer, Capturing and Triggering
				Link Training, the First Step in Communication
				Slot Connector vs. Mid-Bus Pad
				Exercising: In-Depth Verification
				Signal Integrity, Design and Measurement
			Appendix B.  Markets & Applications for the PCI Express™ Architecture
				Introduction
				Enterprise Computing Systems
				Embedded Control
				Storage Systems
				Communications Systems
				Summary
			Appendix C.  Implementing Intelligent Adapters and Multi-Host Systems With PCI Express™ Technology
				Introduction
				Usage Models
				The History Multi-Processor Implementations Using PCI
				Implementing Multi-host/Intelligent Adapters in PCI Express Base Systems
				Summary
				Address Translation
			Appendix D.  Class Codes
			Appendix E.  Locked Transactions Series
				Introduction
				Background
				The PCI Express Lock Protocol
				Summary of Locking Rules
		Index

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